1. Field of the Invention
The invention relates to a differential input circuit and, more particularly, to a differential input circuit which is suitable for use in an interface portion such as SSTL-3 (Stub Series Terminated Logic for 3.3V) that is used in an IC circuit.
2. Description of the Related Art
In recent years, a performance of a CPU which is used in a computer or the like has remarkably been improved, and a CPU which operates at a high frequency of 100 MHz or higher is also provided. To raise an operating frequency of the CPU, an amplitude of a signal voltage is so small to be, for example, about 0.4V. In an IC circuit which needs an operating voltage of about 3V, therefore, it is necessary that an input voltage of a small amplitude which is supplied from the CPU through a system bus or the like needs to be amplified to a predetermined level. A differential input circuit is used to amplify the input voltage.
As shown in FIG. 1, a conventional differential input circuit includes two NMOS transistors N11 and N12 having the same characteristics and two PMOS transistors P11 and P12 having the same characteristics (Refer to Itoh, "Super LSI memory", Baifukan Co., Ltd., p. 67, 1994). An input voltage Vin of a small amplitude is inputted to a gate of the NMOS transistor N11. A reference voltage Vref is inputted to a gate of the NMOS transistor N12. Sources of the two NMOS transistors N11 and N12 are connected to the ground. A drain of the NMOS transistor N11 is connected to a drain of the PMOS transistor P11. A drain of the NMOS transistor N12 is connected to a drain of the PMOS transistor P12. Gates of the two PMOS transistors P11 and P12 are mutually connected and are also connected to the drain of the NMOS transistor N11 and the drain of the PMOS transistor P11. A power voltage Vdd is supplied to sources of the two PMOS transistors P11 and P12. An output voltage Vout is derived from the drain of the NMOS transistor N12.
The differential input circuit is a circuit to which a general differential amplifying circuit of a current mirror type is applied and the output voltage Vout is obtained by amplifying a difference voltage between the input voltage Vin and reference voltage Vref. For example, as shown in FIG. 2, when the reference voltage Vref is set to a fixed voltage of 1.2V and the input voltage Vin is a pulse-like voltage which fluctuates at an amplitude of .+-.0.4V for a DC voltage of 1.2V, since the reference voltage Vref is the fixed voltage, an amplitude of the output voltage Vout is determined by a gain of the input voltage Vin. That is, the output voltage Vout that is proportional to the input voltage Vin is derived from the differential input circuit.
In a general differential amplifying circuit, both of the sources of the two NMOS transistors N11 and N12 are connected to the ground through a transistor, a constant current source, or the like. However, as shown in FIG. 2, when one of the two input voltages is a fixed voltage, there is a case where when the sources of the two NMOS transistors N11 and N12 are connected to the ground through the transistor, constant current source, or the like, the differential amplifying circuit does not operate normally. In the differential input circuit shown in FIG. 1, therefore, both of the sources of the two NMOS transistors N11 and N12 are directly connected to the ground.
In a present situation in which the operating speed of the CPU is high as mentioned above, since it is also necessary to improve a response speed of the IC circuit in association with it, it is necessary that the level of the output voltage which is obtained by the differential input circuit reaches about 3V as a necessary voltage level of the IC circuit as soon as possible.
In the differential input circuit of FIG. 1, however, as shown in FIG. 2, a leading slope of the output voltage Vout is gentle and it takes a too long time until the output voltage reaches about 3V as a necessary voltage level of the IC circuit.
As an example of a construction of a differential input circuit in which a leading time of the output voltage is short, as shown in FIG. 3, there is a circuit of a push-pull type of two stages using three differential input circuits shown in FIG. 1 (refer to Itoh, "Super LSI Memory", Baifukan Co., Ltd., p. 68, 1994). For convenience of explanation, the differential input circuit shown in FIG. 1 is called a "differential circuit" hereinafter.
The differential input circuit includes: a first differential circuit 1; a second differential circuit 2; a third differential circuit 3; an NMOS transistor N4 provided between the first and second differential circuits 1 and 2 and the ground; and an NMOS transistor N5 provided between the third differential circuit 3 and the ground. A drain of the NMOS transistor N4 is connected to the sources of the two NMOS transistors N11 and N12 of the first differential circuit 1 and sources of two NMOS transistors N21 and N22 of the second differential circuit 2. A source of the NMOS transistor N4 is connected to the ground. The power voltage Vdd is inputted to a gate of the NMOS transistor N4. A drain of the NMOS transistor N5 is connected to sources of two NMOS transistors N31 and N32 of the third differential circuit 3. A source of the NMOS transistor N5 is connected to the ground. The power voltage Vdd is inputted to a gate of the NMOS transistor N5.
In the differential input circuit, the input voltage Vin is inputted to the gate of the NMOS transistor N11 of the first differential circuit 1. The reference voltage Vref is inputted to a gate of the NMOS transistor N21 of the second differential circuit 2 corresponding to the NMOS transistor N11 of the first differential circuit 1. The reference voltage Vref is inputted to the gate of the NMOS transistor N12 of the first differential circuit 1. The input voltage Vin is inputted to a gate of the NMOS transistor N22 of the second differential circuit 2 corresponding to the NMOS transistor N12 of the first differential circuit 1. That is, the first and second differential circuits 1 and 2 are symmetrically connected with respect to the input voltage Vin and reference voltage Vref. Therefore, a first differential voltage V1 which is outputted from the drain of the NMOS transistor N12 of the first differential circuit 1 and a second differential voltage V2 which is outputted from a drain of the NMOS transistor N22 of the second differential circuit 2 have opposite phases.
The first differential voltage V1 is inputted to a gate of the NMOS transistor N32 of the third differential circuit 3. The second differential voltage V2 is inputted to a gate of the NMOS transistor N31 of the third differential circuit 3. Thus, the output voltage Vout which is proportional to the difference voltage between the first and second differential voltages V1 and V2 is derived (refer to FIG. 4).
Since both the first and second differential voltages V1 and V2 which are inputted to the third differential circuit 3 are not fixed voltages, the sources of the two NMOS transistors N31 and N32 can be connected to the ground through a transistor, a constant current source, or the like in a manner similar to an ordinary differential amplifying circuit. In the differential input circuit, the sources of the two NMOS transistors N31 and N32 are connected to the ground through the NMOS transistor N5. In the differential input circuit, since the sources of the two NMOS transistors N11 and N12 of the first differential circuit 1 and the sources of the two NMOS transistors N21 and N22 of the second differential circuit 2 can be also connected to the ground through a transistor, a constant current source, or the like, they are connected to the ground through the NMOS transistor N4.
However, in the differential input circuit shown in FIG. 3, as compared with the differential input circuit shown in FIG. 1, a leading slope of the output voltage Vout can be made slightly sharp. However, an improvement of the leading slope of the output voltage Vout is insufficient. That is, when levels of the first and second differential voltages V1 and V2 are changed in association with a trailing edge of the input voltage Vin shown in a time interval from a time of 0.25 nsec to a time of 26 nsec in FIG. 4, since a trailing slope of the first differential voltage V1 is gentle, a leading time of the output voltage Vout is long. With regard to the improvement of the tailing time of the output voltage Vout as well, it is insufficient because of a similar reason.